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datasheet 9DBV0631 revision e 09/11/14 1 ?2014 integrated device technology, inc. 6 o/p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 description the 9DBV0631 is a member of idt's 1.8v very-low-power (vlp) pcie family. the device has 6 output enables for clock management and 3 selectable smbus addresses. recommended application 1.8v pcie gen1-2-3 zero delay/fanout buffer (zdb/fob) output features ? 6 - 1-200 mhz low-power (lp) hcsl dif pairs key specifications ? dif additive cycle-to-cycle jitter <5ps ? dif output-to-output skew <60ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms for sgmii features/benefits ? lp-hcsl outputs; save 12 resistors compared to standard pcie devices ? 55mw typical power consumption in pll mode; minimal power consumption ? outputs can optionally be supplied from any voltage between 1.05 and 1.8v; maximum power savings ? oe# pins; support dif power management ? hcsl-compatible differential input; can be driven by common clock sources ? spread spectrum tolerant; allows reduction of emi ? programmable slew rate for each output; allows tuning for various line lengths ? programmable output amplitude; allows tuning for various application environments ? pin/software selectable pl l bandwidth and pll bypass; minimize phase jitter for each application ? outputs blocked until pll is locked; clean system start-up ? configuration can be accomplished with strapping pins; smbus interface not required for device control ? 3.3v tolerant smbus inte rface works with legacy controllers ? space saving 40-pin 5x5mm mlf; minimal board space ? 3 selectable smbus addresses; multiple devices can easily share an smbus segment block diagram control logic ^vhibw_bypm_lobw# ^ckpwrgd_pd# sdata_3.3 ss- compatible pll voe(5:0)# sclk_3.3 vsadr clk_in c l k _ i n # 6 dif5 dif4 dif3 dif2 dif1 dif0
6 o/p 1.8v pcie gen1-2-3 zdb/fob 2 revision e 09/11/14 9DBV0631 datasheet pin configuration smbus address selection table power management table ^ckpwrgd_pd# vddio voe5# dif5# dif5 voe4# dif4# dif4 vddio vdd1.8 40 39 38 37 36 35 34 33 32 31 vsadr_tri 130 nc ^vhibw_bypm_lobw# 229 voe3# fb_dnc 328 dif3# fb_dnc# 427 dif3 vddr1.8 526 vddio clk_in 625 vdda1.8 clk_in# 724 voe2# gnddig 823 dif2# sclk_3.3 922 dif2 sdata_3.3 10 21 voe1# 11 12 13 14 15 16 17 18 19 20 vdddig1.8 vddio voe0# dif0 dif0# vdd1.8 vddio dif1 dif1# nc 40-vfqfpn ^ pref ix indicates internal pull-up resistor v prefix indicates internal pull-dow n resistor 5mm x 5mm 0.4mm pin pitch 9DBV0631 paddle is gnd sadr address 0 1101011 m 1101100 1 1101101 x x x state of sadr on first application of ckpwrgd_pd# + read/write bit true o/p comp. o/p 0 x x x low low off 1 running 0 x low low on 1 1 running 1 0 running running on 1 1 running 1 1 low low on 1 clk_in difx oex# pin pll ckpwrgd_pd# smbus oex bit 1. if bypass mode is selected, the pll will be off, and outputs will follow this table.
revision e 09/11/14 3 6 o/p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet power connections frequency select table pll operating mode pin number vdd vddio gnd 541 input receiver analo g 11 8 digital power 16, 31 12,17,26,32, 39 41 dif outputs, lo g ic 25 41 pll analog description fsel b y te3 [ 1:0 ] clk_in ( mhz ) difx ( mhz ) 00 100.00 clk_in 01 50.00 clk_in 10 125.00 clk_in 11 reserved reserved hibw_bypm_lobw# mode byte1 [7:6] readback byte1 [4:3] control 0 pll lo bw 00 00 m bypass 01 01 1 pll hi bw 11 11
6 o/p 1.8v pcie gen1-2-3 zdb/fob 4 revision e 09/11/14 9DBV0631 datasheet pin descriptions pin # pin name pin type description 1 vsadr_tri latched in tri-level latch to select smbus address. see smbus address selection table. 2 ^vhibw_bypm_lobw# latched in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 3 fb_dnc dnc true clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 4 fb_dnc# dnc complement clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 5 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differential reference clock. 7 clk_in# in complementary input for differential reference clock. 8 gnddig gnd ground pin for digital circuitry 9 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 10 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 11 vdddig1.8 pwr 1.8v digital power (dirty power) 12 vddio pwr power supply for differential outputs 13 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 14 dif0 out differential true clock output 15 dif0# out differential complementary clock output 16 vdd1.8 pwr power supply, nominal 1.8v 17 vddio pwr power supply for differential outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 nc n/a no connection. 21 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 vdda1.8 pwr 1.8v power for the pll core. 26 vddio pwr power supply for differential outputs 27 dif3 out differential true clock output 28 dif3# out differential complementary clock output 29 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 nc n/a no connection. 31 vdd1.8 pwr power supply, nominal 1.8v 32 vddio pwr power supply for differential outputs 33 dif4 out differential true clock output 34 dif4# out differential complementary clock output 35 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 36 dif5 out differential true clock output 37 dif5# out differential complementary clock output 38 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 39 vddio pwr power supply for differential outputs 40 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 41 epad gnd connect paddle to ground.
revision e 09/11/14 5 6 o/p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet test loads driving lvds alternate differential output terminations rs zo units 33 100 27 85 ohms rs rs low-power differential output test load 2pf 2pf 5 inches zo=100w ? lvds clk input l4 r8b r7b r8a r7a 3.3 volts cc cc rs rs driving lvds driving lvds inputs receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
6 o/p 1.8v pcie gen1-2-3 zdb/fob 6 revision e 09/11/14 9DBV0631 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9dbv063 1. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect pr oduct reliability. electrical parame ters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes supply voltage vddx -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.5 v 1,3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t amb ; supply voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input high voltage - dif_in v i hdi f differential inputs (single-ended measurement) 300 750 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 200 725 mv 1 input amplitude - dif_in v swing peak to peak value (v i hdi f - v ildi f ) 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.35 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 150 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
revision e 09/11/14 7 6 o/p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb , voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddx supply voltage for core and analog 1.7 1.8 1.9 v output supply voltage vddio supply voltage for low power hcsl outputs 0.95 1.05-1.8 1.9 v commmercial r ange 0 25 70 c 1 industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.6 v dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua f ib yp bypass mode 1 200 mhz 2 f i p ll 100mhz pll mode 60 100.00 110 mhz 2 f i p ll 125mhz pll mode 75 125.00 137.5 mhz 2 f i p ll 50mhz pll mode 30 50.00 55 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,6 c ou t output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency pcie f modi npci e allowable frequency for pcie applications (triangular modulation) 30 33 khz input ss modulation frequency non-pcie f modi n allowable frequency for non-pcie applications (triangular modulation) 066khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.8 v 4 smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 5 smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb bus voltage 1.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 7 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until outputs are >200 mv 4 for v ddsmb < 3.3v, v ilsmb <= 0.35v ddsmb 5 for v ddsmb < 3.3v, v ihsmb >= 0.65v ddsmb 6 dif_in input 7 the differential input clock must be running for the smbus to be active ambient operating temperature t amb input current input frequency capacitance
6 o/p 1.8v pcie gen1-2-3 zdb/fob 8 revision e 09/11/14 9DBV0631 datasheet electrical characteristics? low-power hcsl outputs electrical characteristi cs?current consumption ta = t amb ; supply voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes dv/dt scope averaging on, fast setting 1.7 2.9 4 v/ns 1,2,3 dv/dt scope averaging on, slow setting 1.1 2.1 3.4 v/ns 1,2,3 slew rate matching dv/dt slew rate matching, scope averaging on 7 20 % 1,2,4 voltage high v hi gh 660 774 850 7 voltage low v low -150 18 150 7 max voltage vmax 821 1150 7 min voltage vmin -300 -15 7 vswing vswing scope averaging off 300 1536 mv 1,2 crossing voltage (abs) vcross_abs scope averaging off 250 414 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 13 140 mv 1,6 2 measured from differential waveform 7 at default smbus settings. slew rate statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. ta = t amb ; supply voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i dda vdda+vddr, pll m ode, @100mhz 11 15 ma 1 i dd vdd, all outputs active @100mhz 610 ma 1 i ddo vddio, all outputs active @100mhz 24 30 ma 1 i ddapd vdda+vddr, ckpwrgd_pd#=0 0.4 0.6 ma 1, 2 i ddpd vdd, ckpwrgd_pd#=0 0.5 0.8 ma 1, 2 i ddopd vddio, ckpwrgd_pd#=0 0.0003 0.1 ma 1, 2 1 guaranteed by design and characterization, not 100% tested in production. 2 input clock stopped. operating supply current powerdown current
revision e 09/11/14 9 6 o/p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics electrical characteristics? phase jitter parameters ta = t amb ; supply voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes -3db point in high bw mode 1.8 2.7 3.8 mhz 1,5 -3db point in low bw mode 0.8 1.4 2 mhz 1,5 pll jitter peaking t jpeak peak pass band gain 1.1 2 db 1 duty cycle t d c measured differentially, pll mode 45 50.1 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -1 0.0 1%1,3 t p dbyp bypass mode, v t = 50% 3000 3636 4500 ps 1 t p dpll pll mode v t = 50% 0 81 200 ps 1,4 skew, output to output t sk3 v t = 50% 26 50 ps 1,4 pll mode 13 50 ps 1,2 additive jitter in bypass mode 0.1 5ps1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform 3 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 4 all outputs at default slew rate 5 the min/typ/max values of each bw setting track each other, i.e., low bw max will never occur with hi bw min. skew, input to output jitter, cycle to cycle t jcyc-cyc pll bandwidth bw ta = t amb ; supply voltage per vdd, vddio of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jp hpcieg1 pcie gen 1 31 52 86 ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.8 1.4 3 ps (rms) 1,2,3,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.3 2.5 3.1 ps (rms) 1,2,3,5 t jphpcieg3 pcie gen 3 common clock architecture (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.5 0.6 1 ps (rms) 1,2,3,5 t jphpcieg3srn s pcie gen 3 separate reference no spread (srns) (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.5 0.6 0.7 ps (rms) 1,2,3,5 t jphsgmii 125mhz, 1.5mhz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 1.9 2n/a ps (rms) 1,2,3,5 t jphpcieg1 pcie gen 1 0.1 5 n/a ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.4 n/a ps (rms) 1,2,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.10 0.3 n/a ps (rms) 1,2,5 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.00 0.1 n/a ps (rms) 1,2,4,5 t jphsgmiim0 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 165 200 n/a fs (rms) 1,6 t jphsgmiim1 125mhz, 12khz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 251 300 n/a fs (rms) 1,6 1 guaranteed by design and characterization, not 100% tested in production. 4 for rms fi g ures, additive jitter is calculated by solvin g the followin g equation: additive jitter = sqrt[(total jitter)^2 - (input jitter)^2] 5 driven by 9fgv0831 or equivalent 6 rohde&schartz sma100 additive phase jitter t jphpcieg2 2 see htt p ://www. p cisi g .com for com p lete s p ecs 3 sam p le size of at least 100k c y cles. this fi g ures extra p olates to 108 p s p k- p k @ 1m c y cles for a ber of 1-12. phase jitter, pll mode t jphpcieg2
6 o/p 1.8v pcie gen1-2-3 zdb/fob 10 revision e 09/11/14 9DBV0631 datasheet additive phase jitter: 125m (12khz to 20mhz) rms additive jitter: 251fs
revision e 09/11/14 11 6 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: read/write addre ss is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
6 o/p 1.8v pcie gen1-2-3 zdb/fob 12 revision e 09/11/14 9DBV0631 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe5 output enable rw low/low enabled 1 bit 6 dif oe4 output enable rw low/low enabled 1 bit 5 1 bit 4 dif oe3 output enable rw low/low enabled 1 bit 3 dif oe2 output enable rw low/low enabled 1 bit 2 dif oe1 output enable rw low/low enabled 1 bit 1 1 bit 0 dif oe0 output enable rw low/low enabled 1 1. a low on these bits will overide the oe# pin and force the differential output low/low smbus table: pll operating mode and output amplitude control register byte 1 name control function type 0 1 default bit 7 pllmoderb1 pll mode readback bit 1 r latch bit 6 pllmoderb0 pll mode readback bit 0 r latch bit 5 pllmode_swcntrl enable sw control of pll mode: rw values in b1[7:6] set pll mode values in b1[4:3] set pll mode 0 bit 4 pllmode1 pll mode control bit 1 rw 1 0 bit 3 pllmode0 pll mode control bit 0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 slewratesel dif5 adjust slew rate of dif5 rw slow setting fast setting 1 bit 6 slewratesel dif4 adjust slew rate of dif4 rw slow setting fast setting 1 bit 5 1 bit 4 slewratesel dif3 adjust slew rate of dif3 rw slow setting fast setting 1 bit 3 slewratesel dif2 adjust slew rate of dif2 rw slow setting fast setting 1 bit 2 slewratesel dif1 adjust slew rate of dif1 rw slow setting fast setting 1 bit 1 1 bit 0 slewratesel dif0 adjust slew rate of dif0 rw slow setting fast setting 1 smbus table: frequency select control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 freq_sel_en enable sw selection of frequency rw sw frequency change disabled sw frequency change enabled 0 bit 4 fsel1 freq. select bit 1 rw 1 0 bit 3 fsel0 freq. select bit 0 rw 1 0 bit 2 1 bit 1 1 bit 0 slewratesel fb adjust slew rate of fb rw slow setting fast setting 1 1. b3[5] must be set to a 1 for these bits to have any effect on the part. byte 4 is reserved and reads back 'hff reserved reserved controls output amplitude reserved reserved reserved reserved see frequency select table reserved reserved reserved see pll operating mode table see pll operating mode table
revision e 09/11/14 13 6 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 1 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 1 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 reserved reserved byte count programming writing to this register will configure how many bytes will be read back, default is = 8 bytes. reserved revision id a rev = 0000 vendor id 0001 = idt device type 00 = fg, 01 = db 10 = dm, 11= db fanout only device id 000110 binary or 06 hex
6 o/p 1.8v pcie gen1-2-3 zdb/fob 14 revision e 09/11/14 9DBV0631 datasheet marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes co untry of origin. 3. ?yyww? is the last two digits of the year and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. thermal characteristics ics bv0631bl yyww coo lot ics v0631bil yyww coo lot parameter symbol conditions pkg typ value units notes jc junction to case 42 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 1 epad soldered to board thermal resistance ndg40
revision e 09/11/14 15 6 o/ p 1.8v pcie gen1-2-3 zdb/fob 9DBV0631 datasheet package outline and package dimensions (ndg40) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number are the pb-free configuration and are rohs compliant. ?b? is the device revision designator (will not correlate with the datasheet revision). millimeters symbol min max a 0.80 1.00 a1 0 0.05 a3 0.20 reference b 0.18 0.30 e 0.40 basic n40 n d 10 n e 10 d x e basic 5.00 x 5.00 d2 3.55 3.80 e2 3.55 3.80 l 0.30 0.50 sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 ep ? exposed thermal pad should be externally connected part / order number shipping packaging package temperature 9DBV0631bklf trays 40-pin vfqfpn 0 to +70 c 9DBV0631bklf tape and reel 40-pin vfqfpn 0 to +70 c 9DBV0631bkilf trays 40-pin vfqfpn -40 to +85 c 9DBV0631bkilf tape and reel 40-pin vfqfpn -40 to +85 c
6 o/p 1.8v pcie gen1-2-3 zdb/fob 16 revision e 09/11/14 9DBV0631 datasheet revision history rev. intiator issue date description page # a rdw 9/5/2012 1. pinout changed from 48 to 40 pins. paddle is now gnd 2. thermal data added 3. general description/front page text updated to match other 9dbvxx31 devices. 4. smbus updated. 5. power ground connections updated. 6. electrical tables updated. 7. move to preliminary. various b rdw 9/17/2012 1. changed ordering information from 9DBV0631a to 9DBV0631b c rdw 2/25/2013 1. changed vih min. from 0.65*vdd to 0.75*vdd 2. changed vil max. from 0.35*vdd to 0.25*vdd 3. added missing mid-level input voltage spec (vim) of 0.4*vdd to 0.6*vdd. 6 d s.l. 7/7/2014 updated top-side deive marking and associated notes. 12 e rdw 9/10/2014 1. updated front page text for consistency. 2. updated block diagram for consistency. 3. updated electrical tables with characterization data. 4. updated smbus nomenclature - bits did not change. 5. converted to new doc template. 6. changed idd spec from 8ma to 10ma max. various
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